Webinar – What You Need to Know Before Simulating DDR5 Buses

<p><!-- wp:heading --></p> <h2>Summary</h2> <p><!-- /wp:heading --></p> <p><!-- wp:paragraph --></p> <p>The insatiable desire for more bandwidth in data centers has led to intense pressure to push DDR5 memory technology out to market faster.  During this webinar you will learn what you need to know before simulating DDR5 buses. </p> <p><!-- /wp:paragraph --></p> <p><!-- wp:list --></p> <ul> <li>What are the changes from DDR4 to DDR5, and why new simulation and measurement techniques are necessary?   </li> <li>How channel simulation technology (using IBIS-AMI modeling) has been adapted specifically for single-ended signals with an external clock.   </li> <li>How to apply the new simulation technology within productive and predictive DDR5 workflow using PathWave ADS with Memory Designer </li> </ul> <p><!-- /wp:list --></p>